1. Field of the Invention
This invention relates to a method of fabricating infrared detectors and the detector.
2. Brief Description of the Prior Art
Infrared detectors using HgCdTe area arrays generally utilize HgCdTe photodiodes as optical detectors with the photodiodes being interconnected with silicon processing stages. Such infrared detectors are generally fabricated at temperatures greater than room temperatures but are operated at cryogenic temperatures in the range of liquid nitrogen or liquid helium.
Infrared detectors of the prior art are exemplified by Simmons U.S. Pat. No. 4,720,738 and Schulte U.S. Pat. No. 4,447,291, the specifications of which are incorporated herein by reference, wherein vertically integrated infrared detector semiconductor elements are directly coupled to an underlying silicon signal processing chip and rest on the surface of the underlying chip. This arrangement presents several problems. For example, the surface roughness caused by the non-planar surface topology of the fabricated silicon signal processing chip induces crystal defects in the infrared detector semiconductor when the detector and processing chip are pressed together during the attachment step of the fabrication process. This leads to a yield diminution. Also, the silicon signal processing chip and the infrared detector semiconductor have different thermal expansion coefficients. They are attached together at temperatures greater than room temperature, but cooled far below room temperature during actual operation. The thermal expansion mismatch induces stress in the infrared detector semiconductor which can cause failure in the field. Additionally, the infrared detector is attached to the silicon signal processing chip early in the fabrication sequence. Therefore the silicon chip must be present during the detector fabrication sequence with subsequent yield loss due to handling, chemical attack, electrical overstress, etc. Furthermore, most of the area of a completed vertically integrated MIS detector is taken up by the signal processing circuitry. The relatively small detector array is located in the middle of this circuitry. During fabrication, a single piece of detector semiconductor is mounted on the silicon signal processing substrate in order to cover as many detector array areas as possible. In spite of this method of maximizing the number of detector arrays from each piece of detector semiconductor, the absolute utilization of detector semiconductor is low. It is therefore desirable to eliminate or minimize each of the above noted problems encountered in the prior art.